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Minimizing the Delay of C2MOS D Flip Flop using Logical Effort Theory | Abstract
Journal of Remote Sensing & GIS

Journal of Remote Sensing & GIS
Open Access

ISSN: 2469-4134

+32 25889658

Abstract

Minimizing the Delay of C2MOS D Flip Flop using Logical Effort Theory

Swarnima Trivedi

Future Electronics has a full selection of Binary counters or Frequency dividers such as Radio Frequency divider, digital frequency divider, analog frequency divider which can further be used for improving the performance of electronic counter measures equipment’s, communications systems and laboratory instruments. An arrangement of D Flip Flops is a classical method of designing a Frequency Divider. There is vast variation encountered in digital circuits because of scaling and process imperfections. So this paper deals with D flip-flop circuit in terms of propagation delay. The task is to minimize the propagation delay of D flip-flop blocks using Logical Effort Theory which is further used in designing binary counter.

Published Date: 2021-09-24;

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