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Minimizing the Delay of Binary Counter Designed by C2MOS Technique Using Logical Effort Theory | Abstract
Journal of Information Technology & Software Engineering

Journal of Information Technology & Software Engineering
Open Access

ISSN: 2165- 7866

Abstract

Minimizing the Delay of Binary Counter Designed by C2MOS Technique Using Logical Effort Theory

Swarnima Trivedi

Future Electronics has a full selection of Binary counters or Frequency dividers such as Radio Frequency divider, digital frequency divider, analog frequency divider which can further be used for improving the performance of electronic counter measures equipment’s, communications systems and laboratory instruments. An arrangement of D Flip Flops is a classical method of designing a Frequency Divider. The task for this paper is to minimize the propagation delay of C2MOS D flip-flop blocks using Logical Effort Theory which is further used in designing binary counter.

Published Date: 2021-09-27;

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